Logical Time and Temporal Logics: Comparing UML MARTE/CCSL and PSL

Abstract

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) has been recently adopted. The Clock Constraint Specification Language (CCSL) allows the specification of causal, chronological and timed properties of MARTE models. Due to its purposely broad scope of use, CCSL has an expressiveness that can prevent formal verification. However, when addressing hardware electronic systems, formal verification is an important step of the development. The IEEE Property Specification Language (PSL) provides a formal notation for expressing temporal logic properties that can be automatically verified on electronic system models. In this paper, we determine the part of MARTE/CCSL amenable to support the classical analysis methods from the Electronic Design Automation (EDA) community by comparing \ccsl and PSL expressiveness. We show that neither of these languages is subsumed by the other one. We identify and restrict the CCSL constructs that cannot be expressed in temporal logics so that \ccsl become tractable in temporal logics. Conversely, we also identify the class of PSL formulas that can be encoded in CCSL. We define translations between these fragments of CCSL and PSL using automata as an intermediate representation.