A scalable hardware/software co-design for elliptic curve cryptography on PicoBlaze microcontroller

Abstract

In this paper, we investigate the potential of a hardware/software co-design methodology to realize a low resources scalable elliptic curve cryptography (ECC) processor over binary finite fields GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) on an FPGA platform. The software is hosted on a free-soft-core processor from Xilinx FPGA (PicoBlaze); while two novel arithmetic circuits serve as the hardware environment to perform multi-precision arithmetic and scalable reduction. The proposed design is capable to work over a suite of curves recommended by NIST, namely, m= 163, 233, 283, 409, 571 without reconfiguring either the software or hardware. The proposed architecture is parameterized for data widths 8, 16, 32 bit to evaluate performance versus area trade-offs. The implementation of the scalable ECC processor consumes only 452 (58%) and 559 (72%) slices of the lowest cost chips from Xilinx Spartan III namely XC3S50 for 8 and 16-bits data paths, and 1127 (60%) slices for 32-bit data path on Spartan III XC3S200. Such design developed on FPGA is ideal for System-on-Chip (SOC) integration or can operate as a standalone processor for low-resource applications requiring strong security.