A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

Abstract

A 53.5-62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) of -10.3~ -19.5 dB, output return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> ) of -13.8~ -27.8 dB, forward gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) of 8.1~ 11.1 dB, and reverse isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> ) of -49.9~ -60.2 dB over the 53.5-62-GHz-band. The minimum NF (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21-max</sub> ) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.