Embedded Vision Modules for Tracking and Counting People

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper shows the algorithm implementation for a field-programmable gate array (FPGA)-based design for people counting using a low-level head-detection method. The hardware (HW) implementation on an FPGA allows the capture and online processing in real time on the same chip. Different annular patterns are used to process in parallel the image and detect heads of different sizes. Preprocessing and edge extraction are also made using reconfigurable HW. The developed system exploits HW processing, as the vision algorithm has been modified and tuned for HW implementation. It uses minimal area resources of a Spartan3 (1.5 Mgates), and its real-time performance is comparable with more sophisticated algorithms while utilizing very low cost circuits. </para>