A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

TLDR

The transceiver, fabricated in 0.13 µm CMOS, integrates a fully reconfigurable SDR with RX, TX, two synthesizers, a programmable baseband that adjusts noise level and bandwidth from 350 kHz to 23 MHz, and consumes 62–120 mA in RX mode and 56–89 mA in TX mode from a 1.2 V supply. A MEMS‑enabled dual‑band LNA demonstrates switched‑antenna filtering for interference robustness, while the receiver achieves 6 dB noise figure, –9 dBm IIP3, and up to 90 dB gain.

Abstract

A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process, it draws 62mA to 120mA in RX mode and 56mA to 89mA in TX mode from a 1.2V supply.