CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications

Abstract

The CMOS nonthreshold logic (NTL) is derived from its bipolar counterpart, which is the fastest bipolar logic, and takes the NOR gate as its basic building gate. It is shown that by applying the nonthreshold principle to CMOS circuits speed performance can be highly improved, but with an increase of DC power consumption. From transient analyses the speed of CMOS NTL is found quite comparable to that of I/sup 2/L (integrated injection logic) or even ECL (emitter-coupled logic) and is about 20-60% better than that of conventional CMOS. Meanwhile, the power-delay product of CMOS NTL is smaller than those of I/sup 2/L and ECL and is nearly the same as that of conventional CMOS operated at high frequency. The nonthreshold principle is applied to the CMOS cascode structure to form the CMOS cascode nonthreshold logic (CNTL), in which there is a tradeoff between speed performance and power dissipation. It is shown from the design of full adders that the CMOS NTL is the fastest of all the static CMOS logic circuits. The speed of the CNTL circuit, although slower than that of the NTL circuit, is still higher than that of the DSL circuit, which is the fastest static circuit proposed so far. The CNTL circuit also has a smaller power-delay product than the DSL circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>