A 20Gb/s Duobinary Transceiver in 90nm CMOS

Abstract

The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of electrical channels. Among the existing solutions, duobinary signaling manifests itself in bandwidth efficiency as (1) its spectrum occupies only half as wide as that of NRZ data; (2) it incorporates the intrinsic roll-off bandwidth of the channel as part of the desired response. The design and experimental verification of a fully-integrated duobinary transceiver in 90nm CMOS is described. The transceiver achieves 20Gb/s error-free transmission over a 40cm Rogers and a 10cm FR4 channels.