IEEE Transactions on Circuits and Systems I Regular Papers · 2014 · 76 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSensorsAnalog Integrated CircuitsCmos Circuit DesignConfigurable Logic BlocksDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos ScalingLeakageSensor Applications
An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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