A digital signal processor for an ANSI standard ISDN transceiver

Abstract

The digital signal processing chip of a two-chip ISDN (integrated services digital network) basic access transceiver based on the ANSI standard 2B1Q code is described. Nonlinear echo cancellation is used to improve the loop coverage. The chip features a multiprocessor architecture, where each processor is optimized for the algorithm used. Full observability of internal signals and adaptive filter coefficients is supported. The device is fabricated in a 1.25- mu m double-level-metal CMOS process with an active area of 47 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>