Quasisaturation effect in high-voltage VDMOS transistors

Abstract

In this paper dealing with the so-called quasisaturation current limitation in high-voltage VDMOS transistors, the authors have given a linear law on the dependence of the on-state conductance on the square-root of the drain bias. A four-section model, taking into account the pinching of the drain epilayer by the space-charge extensions and the current spreading in the bulk, accounts for the quasisaturation phenomenon, and the linear behaviour of the empirical law is well verified. Finally, the scaling-up effects on the high-voltage-device current capability are discussed.