Performance analysis of power optimal PLL design using five-stage CS-VCO in 180nm

Abstract

This paper presents the design of PLL (Phase Locked Loop) using PFD (Phase Frequency Detector) based on 22 transistors TSPC (True Single Phase Clock) D-FF (Flip Flop), Tri-state charge pump (CP), passive loop filter of first order and five- stage CS-VCO (Current Starved VCO) circuit. In such design, large VCO gain with increased lock range from (357MHz-900MHz) and reduced lock time is achieved using first order passive lag loop filter. The oscillation frequency range (431.683 MHz-1.7966 GHz) for VCO is increased due to reduced number of inverter stages and power dissipated by overall PLL is getting improved (7.08mW) with less design cost. Area occupied by such PLL is also reduced. This reduction in area and power is achieved with the help of five-stage CS-VCO instead of LC-Tank VCO and five-stage multiple pass ring VCO [8],[12]. The prototype is simulated using 0.18um CMOS technology with supply voltage of 1.8V. In such context the lock time of 54ns is achieved by properly selecting the design parameters for low pass filter (R and C) with reasonable damping factor (ζ=0.7).