A Model for Wafer Fabrication Dynamics in Integrated Circuit Manufacturing

Abstract

Integrated circuit manufacturing has major operations of fabrication, sort, assembly, and test. The dynamic behavior of these operations can be modeled in terms of a highly structured queueing network. A model is presented of the components and interactions of wafer movements, processing equipment, and process steps. The model considers multiple process flows, fab organization and layout, and equipment properties such as batch size, process time, failure, and repair distributions. The model is implemented as a discrete event simulation and has been used in a number of case studies concerning realistic factory situations. This simulation model is general and can be used to study many types of discrete manufacturing.