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Fast parallel pipelined readout architecture for a completely flash digitizing system with multilevel trigger
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1989
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Massively-parallel ComputingEngineeringHardware AccelerationAdvanced ComputingHigh-performance ArchitectureComputer EngineeringComputer ArchitectureFast ParallelReadout ArchitectureParallel ProgrammingComputer ScienceMultilevel TriggerParallel ComputingData-level Parallelism
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