Memory cell using Modified Field Effect Diode

Abstract

Using spice 9.3, we have modeled (I-V) characteristics of a Modified Field Effect Diode (M-FED) with gate length of 75nm and oxide thickness of 10nm. An SRAM cell (Register) has been designed with the simulated M-FED and has been compared to an SOI-MOSFET based circuit. Simulation results demonstrate that clock frequency applied to a memory cell which is designed with M-FED is more than 2 orders of magnitude larger than that of a comparable SOI-MOSFET, while the access time of the M-FED based memory cell is three orders of magnitude less than the comparable SOI-MOSFET.