Digital Offset Trimming Techniques for CMOS MEMS Accelerometers

Abstract

This paper presents a digital trimming technique for canceling the output offsets caused by sensor mismatches in an accelerometer design. The offset cancellation techniques provide fine trimming steps with higher chip area efficiency compared with that of conventional capacitor array compensation approaches. The accelerometer, fabricated in a 0.18- μm complementary metal-oxide-semiconductor micro-electro-mechanical-system process, containing the micro-mechanical structure and readout circuits, occupies only a 0.64 × 0.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. The chip draws 0.4 mA from a 1.8-V supply. The measured sensitivity is 195 mV/g and the nonlinearity is 0.78% within the ±12 g sensing range. The output noise floor is 150 μg/√{Hz}, corresponding to a 1-g 100-Hz sinusoidal acceleration. The output offset voltage can be trimmed from several tens to several hundreds of millivolts down to several millivolts.