Realization of transmission-gate conditional-sum (TGCS) adders with low latency time

Abstract

Transmission conditional-sum (TGCS) adders realized in a standard 2.5- mu m CMOS technology are discussed. These adders offer short propagation delay and latency time (12.5 ns for 32-b addition) and consume only moderate chip area (i.e. 80*460 mu m/sup 2/ for 1 b in a 32-b adder). They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word lengths. Design and layout techniques are described in detail and experimental data are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>