Optimal 2-D cell layout with integrated transistor folding

Abstract

Folding, a key requirement in high-performance cell layout, implies breaking a large transistor into smaller, equal-sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique FCLZP that integrates folding into the generation of optimal layouts of CMOS cells in the twodimensional (2-D) style. FCLZP is based on integer linear programming (ILP) and precisely formulatm cell width minimization as a O-1 optimization problem. Folding is incorporated into the O-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLZP yields optimal resul@ for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions.