Mixed analogue–digital artificial-neural-network architecture with on-chip learning

Abstract

The authors present a novel artificial-neural-network architecture with on-chip learning capability. The issue of straightforward design-flow integration of an autonomous unit is addressed with a mixed analogue–digital approach, by implementing a charge-based artificial neural network which interacts with digital control and processing units. The circuit architecture and design-flow approach for the case of a Hamming network performing pixel-pattern recognition are described.