4.8 A 28nm x86 APU optimized for power and area efficiency

Kathryn Wilcox, David Akeson, Harry R. Fair, J. Farrell, Dave Johnson, Guhan Krishnan, Hugh Mclntyre, E. J. McLellan, Samuel Naffziger, Russell Schreiber,

2015 · 16 citations · 4 references

Concepts

Abstract

Carrizo (CZ, Fig. 4.8.7) is AMD's next-generation mobile performance accelerated processing unit (APU), which includes four Excavator (XV) processor cores and eight Radeon™ graphics core next (GCN) cores, implemented in a 28nm HKMG planar dual-oxide FET technology featuring 3 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> s of thin-oxide devices and 12 layers of Cu-based metallization. This 28nm technology is a density-focused version of the 28nm technology used by Steamroller (SR) [1] featuring eight 1× metals for dense routing, one 2× and one 4× for low-RC routing and two 16x metals for power distribution.

References

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