Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

TLDR

Optical interconnects have enabled high‑bandwidth CPU‑memory buses, and this optical cache architecture bridges optically connected CPU‑cache schemes with high‑speed optical RAM solutions. The authors aim to demonstrate a 16 GHz physical‑layer optical cache memory with direct‑mapping associativity, and to evaluate its impact as a shared L1 cache in chip multiprocessor workloads. The design employs wavelength‑division multiplexing for address and data words, interconnecting experimentally validated optical building blocks into a four‑line cache each storing two bytes. Physical‑layer simulations confirm functional read/write operations, and comparisons with conventional electronic CMPs show up to 40 % speed‑up and an 84 % reduction in total cache capacity.

Abstract

We demonstrate a 16GHz physical layer optical cache memory architecture for direct mapping associativity, organized in four cache lines with every line being capable of storing two bytes of optical data. WDM formatting of both the memory address and the optical data words is exploited, while the proposed design relies on the interconnection of subsystems that comprise experimentally proven optical building blocks. The performance of the optical cache is evaluated via physical layer simulations showing successful functionality both during Read and Write operation. Going a step further and considering a higher capacity optical cache module, we present its impact when performing with true processor workload benchmarks in Chip Multiprocessor configurations, employed as a L1 cache shared among multiple cores. Its performance is compared with the conventional electronic CMP topology, where dedicated L1 electronic caches and a shared L2 cache are used, showing that the use of optical 16GHz cache can lead to performance speed-up up to 40% while reducing the cache total capacity requirements by 84%. With optical interconnects having already resulted to high-bandwidth CPU-memory bus solutions, our optical cache architecture forms a fully compatible system solution for bridging the gap between optically connected CPU-cache schemes and high-speed optical RAM cell solutions.