Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

Abstract

The Viterbi algorithm is one of the most popular algorithms for decoding convolutional codes. Implementing a high-speed Viterbi decoder is a challenging task due to the recursive iteration of an add-compare-select operation. In this paper, we propose and analyze several optimization techniques to improve the area/performance tradeoffs of high speed Viterbi decoders on Virtex-6 FPGAs. Both Radix-2, Radix-4 and a modified radix-4 add-compare-select units are implemented with these techniques. The implementation reports for a Virtex-6 FPGA indicate that the proposed techniques achieve very efficient designs of Viterbi decoders in terms of performance and area. 360 Mbps are achievable with radix-2 solutions, while radix-4 solutions can achieve 430 Mbps, better than previous state-of-the-art solutions. Higher data rates can only be achieved with other parallelization techniques, like the sliding block method.