A 70–100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link

Abstract

A transmitter and receiver phased array chipset is demonstrated in the range between 70 and 100 GHz using a 0.18 µm SiGe BiCMOS process with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}/f_{MAX}$</tex> </formula> of 240/270 GHz. Each chip comprises four phased array elements with distributed calibration memory and calibrated direct up- and down-conversion mixer chain. Each receive channel has a conversion gain of 33 dB and noise figure of < 7 dB from 75–95 GHz. Each transmit channel has a flat saturated output power of > 5 dBm between 70 and 100 GHz. Both transmitter and receiver arrays operate from 1.5 V and 2.5 V power supplies and consume 1 W each. Using a die-on-PCB prototype with integrated antennas, a wireless link operating at 10 Gb/s (using 16-QAM) or 8.75 Gb/s (using 32-QAM) is demonstrated at a distance of 1-meter with a carrier frequency of 88 GHz.