Optimal interconnect circuits for VLSI

Abstract

THE PROPAGATION DELAY of interconnects is a major factor determining the performance of VLSI circuits, because the RC time constant of interconnects increases very rapidly as chip and interconnect dimensions are scaled aggressively. In this paper a simple model for interconnect time delay, including the effects of scaling transistor, interconnect and chip dimensions will be discussed. To reduce interconnect time delay, properly-scaled multilevel conductors, repeaters, cascaded drivers, and cascaded drivers as repeaters are presented. The delay model yields optimum cross sectional interconnect dimensions and driver/ repeater configurations that can reduce interconnect time delays by more than an order of magnitude