SJ-LDMOS with high breakdown voltage and ultra-low on-resistance

Abstract

A new design concept is proposed to eliminate the substrate-assisted depletion effect in a super-junction (SJ) LDMOS. The key feature of the concept is that a non-uniform N-buried layer is implemented which compensates for the charge interaction between the P-substrate and SJ region, realising high breakdown voltage (>700 V) and ultra-low on-resistance. Furthermore, the proposed device is compatible with smart power technology.