Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Abstract

Low power motion estimation (ME) of H.264/AVC is an important research issue because of the growing mobile applications of H.264/AVC encoder. In this paper, low power cache algorithm and architecture for fast ME of H.264/AVC is proposed in order to replace the conventional search range (SR) memory. With the block translation (BT) cache architecture, search trajectory prediction (STP) prefetching algorithm, and ultra low power cache miss hiding (CMH) strategy, 35% SR memory writing power and 67% SR memory static power are reduced for D1 videos. Combining fast ME with the proposed cache provides the total solution for low power ME hardware.