A scalable neural chip with synaptic electronics using CMOS integrated memristors

TLDR

The paper presents the design and simulation of a scalable neural chip that integrates nanoscale memristor‑based synaptic electronics with CMOS technology. The chip comprises integrate‑and‑fire neurons and STDP synapses, with eight‑level memristor conductance storage, a reconfigurable neuron‑connection topology, and is fabricated in a 90 nm CMOS process using via connections to on‑chip post‑processed memristor arrays, totaling ~16 million transistors and 73 728 memristors. Circuit‑level simulations demonstrate that the chip performs neuronal and synaptic computations with biologically realistic behavior.

Abstract

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.