A 240ps 64b carry-lookahead adder in 90nm CMOS

Abstract

A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply