A new Architecture for two-stage OTA with no-miller capacitor compensation

Abstract

A new Architecture for two-stage Operational Transconductance Amplifier is presented. In this new structure the pole-zero cancellation technique is used to increase the amplifier band width. The proposed architecture uses a very simple circuit implementation scheme to create a feed-forward path in order to make a zero in voltage transfer function. The modularity of the proposed architecture also makes this scheme capable for use in multi-stage amplifier design. The DC-gain of 77dB, Unity-gain-bandwidth of 475 MHz is achieved while the OTA consumes only 5.1mW in standard CMOS 0.18μm technology with 1.8V power supply.