Communication-efficient hardware acceleration for fast functional simulation

TLDR

Functional design verification traditionally relies on logic simulation, which slows as complexity grows, while hardware acceleration can reduce simulation time but introduces a critical communication overhead between the software simulator and accelerator. The paper introduces a new technology to accelerate system verification. The method uses hardware acceleration to offload computation from the simulator and reduces communication overhead by employing burst transfers and parallelism through testbench partitioning. Experiments show a ~40‑fold reduction in communication overhead versus conventional hardware‑accelerated simulation, with preserved cycle accuracy and testbench compatibility.

Abstract

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.