Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Abstract

In the high performance VLSI with multi-layer layout model, the complexity of the global routing problem becomes much high under timing constraints. This paper presents a hierarchical global routing method based on a multi-layer routing model for the high performance standard cell layout. In each hierarchical level, the routes of nets are determined by solving a linear programming problem considering wire-sizing and bufferinsertion under timing constraints. We have implemented the proposed method on a workstation and showed the effectiveness of the method from experimental results.