A 4GHz CT ΔΣ ADC with 70dB DR and −74dBFS THD in 125MHz BW

Abstract

In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused by the quantizer's input capacitance, while a local feedback loop compensates for the quantizer's excess delay. These meas ures allow a high-resolution multi-bit ΔΣ ADC to operate at GHz sampling rates. The bandwidth of this CMOS ΔΣ ADC is 6x wider than the state-of-the-art. Compared to a state-of-the-art pipeline BiCMOS ADC, it achieves similar power efficiency and bandwidth, but it only occupies 0.9mm2 in 45nm CMOS, which is essential for low-cost integration. The 4b 3,a-order CT ΔΣ ADC is sam pled at 4GHz and achieves 70dB DR and -74dBFS THD in a 125MHz BW while consuming 256mW. This prototype enables the use of ΔΣ ADCs in applications such as GSM base-stations and HD video systems.