Realization of sub-10 picosecond switching times in selectively doped (Al,Ga)As/GaAs heterostructure transistors

Abstract

We report gate delay times of less than 10 ps for ring oscillators based on direct coupled FET logic implemented with selectively doped (Al,Ga) As/GaAs heterostructure transistors (SDHTs). The minimum delay time observed was 9.4 ps at 77K with a speed-power product of 42.4 fJ and 1.1 V bias. The gate length the enhancement mode driver FETs was measured to be 0.7 µm. Dual-clocked M/S (master-slave) dividers on the same wafer using dual gate SDHTs operated up to a maximum dividing frequency of 6.3 (13.0) GHz at 300 (77)K.