HDLQ

TLDR

Quantum‑dot cellular automata (QCA) offers a dense, low‑power alternative to CMOS, but requires hierarchical design and system‑level tools to support all design phases. This work introduces HDLQ, an HDL model that describes QCA devices and enables their design evaluation. HDLQ verifies QCA logic, supports fault injection, bidirectional operation, and timing/clocking partitioning, and models defects such as thermodynamic kinks and manufacturing faults. The tool is shown to be applicable for logic and timing verification of various memory circuits.

Abstract

Emerging technologies have attracted a substantial interest in overcoming the physical limitations of CMOS as projected at the end of the Technology Roadmap; among these technologies, quantum-dot cellular automata (QCA) relies on different and novel paradigms to implement dense, low power circuits and systems for high-performance computing. As applicable to existing technologies, a hierarchical process can be utilized to facilitate the design of QCA circuits. Tools and methodologies both at system and physical levels are required to support all design phases. This article presents an HDL model to describe QCA “devices” (also referred elsewhere in the technical literature as building blocks, i.e., majority voter, inverter, wire, crossover) and facilitate the evaluation of their design. This tool, referred to as HDLQ, allows a designer to verify the logic characteristics of a QCA system, while supporting within a design environment different operational mechanisms (such as fault injection) and the unique features of QCA (such as bidirectionality and timing/clocking partitioning). The applicability of this design environment to various memory circuits for logic and timing verification is presented in detail. Various defective conditions for kinks due to thermodynamic effects and permanent faults due to manufacturing defects are considered for injection.