A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

Abstract

A new generation of radio telescopes is achieving unprecedented levels of\nsensitivity and resolution, as well as increased agility and field-of-view, by\nemploying high-performance digital signal processing hardware to phase and\ncorrelate large numbers of antennas. The computational demands of these imaging\nsystems scale in proportion to BMN^2, where B is the signal bandwidth, M is the\nnumber of independent beams, and N is the number of antennas. The\nspecifications of many new arrays lead to demands in excess of tens of PetaOps\nper second.\n To meet this challenge, we have developed a general purpose correlator\narchitecture using standard 10-Gbit Ethernet switches to pass data between\nflexible hardware modules containing Field Programmable Gate Array (FPGA)\nchips. These chips are programmed using open-source signal processing libraries\nwe have developed to be flexible, scalable, and chip-independent. This work\nreduces the time and cost of implementing a wide range of signal processing\nsystems, with correlators foremost among them,and facilitates upgrading to new\ngenerations of processing technology. We present several correlator\ndeployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes\nparameter application deployed on the Precision Array for Probing the Epoch of\nReionization.\n