A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology

TLDR

Teramac, a massively parallel experimental computer built at Hewlett‑Packard Laboratories, demonstrates that even with a 100 % defect rate in chemically synthesized components, large‑scale systems can be assembled into reliable, high‑performance data‑communication networks, implying that future nanoscale computers could rely on extensive memories programmed by defect‑locating tutors. The study shows that Teramac’s defect‑tolerant architecture, featuring high‑bandwidth communication that routes around defects, has significant implications for future nanometer‑scale computing paradigms. Despite containing about 220,000 hardware defects that would cripple a conventional computer, Teramac operated 100 × faster than a high‑end single‑processor workstation in some configurations, underscoring the viability of defect‑tolerant architectures for future nanometer‑scale computing.

Abstract

Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system.