A 16 kbit smart 5 V-only EEPROM with redundancy

Abstract

This paper describes several circuit techniques used in the design of a 5-V-only 16 Kbit EEPROM. The EEPROM uses a two transistor cell based on Fowler-Nordheim tunneling to a floating polysilicon gate. The EEPROM features 5-V-only operation, a self-timed program cycle with automatic erase before write, address and data latches, and a `ready' line output. These features make the program cycle timing compatible with static RAMs and simplifies the microprocessor interface. A new redundancy technique using EE cells as the programming element is also described.