Top-Gate Staggered Amorphous Silicon Thin-Film Transistors: Series Resistance and Nitride Thickness Effects

Abstract

Top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated over large-area glass substrates using a selective phosphorus-treatment (PT) of indium-tin-oxide (ITO) source/drain electrodes. The ohmic contact between a-Si:H and ITO had a specific contact resistivity of about 0.18 Ω·cm 2 . For a 100-µm channel length TFT, the source/drain series resistance contributes less than 5% of the total drain-to-source resistance. This contribution increases to about 25% for a 10-µm channel length TFT. Our study also indicated that the interface quality of a-Si:H/a-SiN x :H is amorphous silicon nitride (a-SiN x :H) and a-Si:H thickness independent and dependent, respectively. Effective interface state densities of about 1.5×10 12 cm -2 eV -1 and 3.2×10 12 cm -2 eV -1 were obtained for top-gate TFTs with a 1300 and 300 Å thick a-Si:H films, respectively. Channel conductance activation energy of about 0.1 eV was measured for this top-gate TFT with 300 Å a-Si:H.