A hybrid Chaos-AES encryption algorithm and its impelmention based on FPGA

Abstract

In this paper, a hybrid encryption algorithm is proposed. The proposed algorithm combines between AES and Chaos encryption. The proposed algorithm uses a 128-bit key to encrypt as much data as the user requires, benefiting from the pseudo-random behavior of chaotic functions. This structure is similar to the AES but it replaces S-box and add round key stage by XOR operation with a 2-D chaotic generator (the Henon Map). The proposed algorithm requires only one round, giving it an advantage in speed over the AES which requires 10 rounds of encryption. It is implemented using VHDL on the Virtex 5 FPGA platform, achieving a 11.577 Gb/s throughput. The NIST SP. 800-22 statistical test suit is applied to Henon function with post-processing. All tests were passed, showing the random properties of the function. Hence, this technique succeeds in offering the required balance between good security as in the AES and high throughput like in regular chaos encryption techniques.