Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs

Abstract

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. As much as FPGAs benefit from the most scaled and advanced technologies, they become more susceptible to transistor aging. In this paper, we investigate the effect of transistor aging on programmable routing resources of FPGAs, by considering different implementations through detailed SPICE simulations. The effects of different parameters, such as wire length, cascaded routing, routing fan-out, signal probability and supply voltage on the aging of routing resources are studied.