Inductance estimation for complicated superconducting thin film structures with a finite segment method

Abstract

A scheme for computing inductances in complex superconducting thin film microcircuits, using the method of finite segments, is presented. The goal is to obtain more accurate inductance estimation as is required in a layout design of high speed superconducting digital circuit investigations. A variety of geometric structures such as short stripline, corner, tee connection and Josephson junction via are discussed. Simulation results for these common inductance elements are given for the HYPRES fabrication process requirements. The database created during these simulations has been used in the development of high speed RSFQ digital devices.