A hardware unification unit

Abstract

The design of a hardware unit that performs unification operation is described and analyzed in this paper. In particular, the hardware unification unit is designed to replace the software "unify" function of an existing (UNSW) Prolog interpreter: at the same time. hardware circuits are used extensively to enhance its performance. Based on the design of the hardware unification unit and the statistics obtained from the software 'unify' function, it is shown that the speed of the hardware unification unit is faster than that of the 'unify" function by an order of magnitude. Because the unification is a fundamental operation of Prolog processing and because the 'unify' function is the most time consuming function during query processing, this hardware unification unit can be used to build high performance Prolog machines.