High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm

Abstract

In this paper a two-staged pipelined architecture of the new SHA-3 (Keccak) algorithm is presented. The core can operate on both one-block and multi-block messages, realizing all possible modes of Keccak. Special effort has been paid and different design alternatives have been studied to derive efficient FPGA implementations in terms of throughput and throughput/area metrics. The proposed core has been implemented in Xilinx Virtex-5, Virtex-6, and Virtex-7 FPGA technologies and achieves significant improvements compared to existing FPGA implementations. Specifically, for Virtex-5 the proposed architecture achieves better throughput and throughput/area results from 45.8% to 248× and from 8.9% up to 17.9×, respectively. Regarding Virtex-6, the improvements in throughput and throughput/area are from 47.2% up to 18.1× and from 8% up to 27.3×, respectively.