IEEE Journal of Solid-State Circuits · 2014 · 28 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsDigital CommunicationMicroelectronicsClock Distribution NetworksCmos Circuit DesignMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsReceiver SystemsReconfigurable System ArchitectureClock Distribution DesignClock Network ArchitectureInductorsJitterJitter ToleranceSensitivityTransceiver ArchitecturesTransceiver Design
This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.
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A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
John W. Poulton, R. Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits · 2007 · 240 citations
Engineering, Computer Engineering, Electrical Engineering +17