A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip

Abstract

This paper proposes a reliability-aware mapping technique for multi applications in networks-on-chip. The proposed technique consists of three main steps: 1) Generating a new core graph enriched by spares, based on a given application core graph, 2) Finding smallest rectangular region to place the given application using a heuristic algorithm, and 3) Searching the specified region into whole NoC, and selecting a region which results minimum overall performance and communication energy. Spare cores are connected to all vertices of application core graph and their edges are weighted by failure probability of processing cores assigned to the application and will be updated during mapping process. Many application core graphs are used to evaluate the proposed technique. The results of 100,000 fault injection experiments show communication energy reduction and performance improvement compared to well-known related techniques in both faulty and fault-free modes.