Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1999 · 22 citations · 5 references
EngineeringNeural Networks (Machine Learning)Basic ArchitectureComputer ArchitectureSocial SciencesAccelerator ArchitectureSpiking Neural NetworksNeuromorphic EngineeringParallel ComputingNeurocomputersCognitive ScienceComputer EngineeringNeuromorphic ComputingComputer ScienceNeural NetworksNervous SystemHardware AccelerationComputational NeuroscienceNeural CircuitsNeuronal NetworkDomain-specific AcceleratorParallel ProgrammingNeuroscienceBrain-like Computing
We present the basic architecture of a Memory Optimized Accelerator for Spiking Neural Networks. The accelerator architecture exploits two novel concepts for an efficient computation of spiking neural networks: weight caching and a compressed memory organization. These concepts allow a further parallelization in processing and reduce bandwidth requirements on accelerator's components. Therefore, they pave the way to dedicated digital hardware for real-time computation of more complex networks of pulse-coded neurons in the order of 10<SUP>6</SUP> neurons. The programmable neuron model which the accelerator is based on is described extensively. This shall encourage a discussion and suggestions on features which would be desirable to add to the current model.
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