A 5mA 0.6¿m CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance

Abstract

A 0.6mum 1.8V 5mA Miller-compensated SoC LDO regulator uses 60pF of capacitance to achieve a worst-case power-supply rejection of -27dB over 50MHz. The entire regulator is shielded from fluctuations in the supply using an NMOS cascode that is biased using a charge pump, voltage reference, and RC filters to maintain low dropout. The RC filter establishes a stable bias for the cascode without a significant impact on the efficiency or bandwidth of the LDO regulator.