Feasibility study and on-chip antenna for fully integrated μRFID tag at 60 GHz in 65 nm CMOS SOI

Abstract

This paper reports the feasibility study of a novel passive tag for μRFID applications in the worldwide available free 60-GHz band. The feasibility analysis indicates that a passive fully-integrated μRFID tag, with on-chip antenna, can be realized in 65-nm SOI CMOS technology at 60 GHz with an operating range of about 20 cm. The 65-nm SOI CMOS technology represents a good candidate due to its better performance in terms of low-losses, low-power consumption and lower leakage current if compared with standard bulk process. The proposed circuit does not require complex package or bonding, thanks to the on-chip antenna, and it does not need battery. The low-cost technology and low-weight and low-area occupation are important features of this μRFID, especially if produced in large scale for the mass-market. Since the design of integrated antennas in silicon technology is one of the main challenge, especially for this proposal, two 60-GHz antennas have been designed by means of 3D-EM simulator: a CPW double-slot antenna and a CPS dipole one. The simulation results show a gain of 4.44 dBi and 3.23 dBi for the proposed double slot and dipole on-chip antennas, respectively.