Transistor level automatic layout generator for non-complementary CMOS cells

Abstract

This paper presents a tool that makes it possible to generate full layouts of CMOS cells from its transistor level netlist in SPICE format. The tool generates the cells under a linear matrix (1I)) similar layout style and is able to support unrestricted circuit structures, continuous transistor sizing and folding. It features a transistor placement algorithm for width reduction that aims the reduction of the number of diffusion gaps and the wirelength of the internal connections. The circuit nets are routed using a negotiation-based algorithm, and an Integer Linear Programming (ILP) solver is used to compaction. The experimental results show that our methodology produces layouts competitive to exact methods. The runtimes were kept low even for cells with more than 30 transistors.