A floorplan-based planning methodology for power and clock distribution in ASICs

Abstract

Article A floorplan-based planning methodology for power and clock distribution in ASICs Share on Authors: Joon-Seo Yim DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, KoreaView Profile , Seong-Ok Bae DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, KoreaView Profile , Chong-Min Kyung Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, Korea Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, KoreaView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 766–771https://doi.org/10.1145/309847.310054Online:01 June 1999Publication History 34citation542DownloadsMetricsTotal Citations34Total Downloads542Last 12 Months12Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access