Asymmetrically strained all-silicon Tunnel FETs featuring 1V operation

Abstract

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> characteristics. We demonstrate that a lateral strain profile with a maximum of strain higher than 3 GPa at the BTB source junction could act as an effective performance Tunnel FET enabling the cancellation of the drain threshold voltage. We study and report in detail the contributions of main technology boosters of all-silicon Tunnel FETs: (i) strained source, (ii) high-k gate dielectric, (iii) multiple-gate, (iv) oxide alignment to i-region and (v) channel length scaling, as an additive device optimization enabling future sub-1 V operation.